Instruction set

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It has been suggested that some sections of this article be split into a new article entitled instruction set architecture. (Discuss)
An instruction set is (a list of) all instructions, and all their variations, that a processor can execute.
Instructions include:
Arithmetic such as add and subtract
Logic instructions such as and, or, and not
Data instructions such as move, input, output, load, and store
Control flow instructions such as goto, if ... goto, call, and return.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), the native commands implemented by a particular CPU design.
Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs.
This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400. TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a virtual machine. It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to recompile any parts of the OS or software associated with it. Nowadays there is several open source Operating Systems which could be easily ported on any existing general purpose CPU, because the compilation is the essential part of their design (e.g. new software installation).
Contents[hide]
1 Instruction set design
1.1 Code density
1.2 Number of operands
1.3 Machine language
2 List of ISAs
2.1 ISAs implemented in hardware
2.2 ISAs commonly implemented in software with hardware incarnations
2.3 ISAs never implemented in hardware
3 See also
3.1 Categories of ISA
3.2 Applications where specialized instruction sets are used
3.3 Device types that implement some ISA
3.4 Others
4 References
5 External links
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[edit] Instruction set design
When designing microarchitectures, engineers use Register Transfer Language (RTL) to define the operation of each instruction of an ISA. Historically there have been 4 ways to store that description inside the CPU:
all early computer designers, and some of the simpler later RISC computer designers, hard-wired the instruction set.
Many CPU designers compiled the instruction set to a microcode ROM inside the CPU. (such as the Western Digital MCP-1600)
Some CPU designers compiled the instruction set to a writable RAM or FLASH inside the CPU (such as the Rekursiv processor and the Imsys Cjip)[1], or an FPGA (reconfigurable computing).
An ISA can also be emulated in software by an interpreter. Due to the additional translation needed for the emulation, this is usually slower than directly running programs on the hardware implementing that ISA. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.
Some instruction set designers reserve one or more opcodes for some kind of software interrupt. For example, MOS Technology 6502 uses 00H, Zilog Z80 uses the eight codes C7,CF,D7,DF,E7,EF,F7,FFH[1] while Motorola 68000 use codes in the range A000..AFFFH.
Fast virtual machines are much easier to implement if an instruction set meets the Popek and Goldberg virtualization requirements.
On systems with multiple processors, non-blocking synchronization algorithms are much easier to implement if the instruction set includes support for something like "fetch-and-increment" or "load linked/store conditional (LL/SC)" or "atomic compare and swap".

[edit] Code density
In early computers, program memory was expensive and limited, and minimizing the size of a program in memory was important. Thus the code density -- the combined size of the instructions needed for a particular task -- was an important characteristic of an instruction set. Instruction sets with high code density employ powerful instructions that can implicitly perform several functions at once. Typical complex instruction-set computers (CISC) have instructions that combine one or two basic operations (such as "add", "multiply", or "call subroutine") with implicit instructions for accessing memory, incrementing registers upon use, or dereferencing locations stored in memory or registers. Some software-implemented instruction sets have even more complex and powerful instructions.
Reduced instruction-set computers (RISC), first widely implemented during a period of rapidly-growing memory subsystems, traded off simpler and faster instruction-set implementations for lower code density (that is, more program memory space to implement a given task). RISC instructions typically implemented only a single implicit operation, such as an "add" of two registers or the "load" of a memory location into a register.
Minimal instruction set computers (MISC) are a form of stack machine, where there are few separate instructions (16-64), so that multiple instructions can be fit into a single machine word. These type of cores often take little silicon to implement, so they can be easily realized in an FPGA or in a multi-core form. Code density is similar to RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.
There has been research into executable compression as a mechanism for improving code density. The mathematics of Kolmogorov complexity describes the challenges and limits of this.

[edit] Number of operands
Instruction sets may be categorized by the number of operands in their most complex instructions. (In the examples that follow, a, b, and c refer to memory addresses, and reg1 and so on refer to machine registers.)
0-operand ("zero address machines") -- these are also called stack machines, and all operations take place using the top one or two positions on the stack. Add two numbers in five instructions: #a, load, #b, load, add, #c, store;
1-operand -- this model was common in early computers, and each instruction performs its operation using a single operand and places its result in a single accumulator register: load a, add b, store c;
2-operand -- most RISC machines fall into this category, though many CISC machines also fall here as well. For a RISC machine (requiring explicit memory loads), the instructions would be: load a, reg1, load b, reg2, add reg1,reg2, store reg2,c;
3-operand CISC -- some CISC machines fall into this category. The above example here might be performed in a single instruction in a machine with memory operands: add a, b,c, or more typically (most machines permit a maximum of two memory operations even in three-operand instructions): move a, reg1, add reg1,b, c;
3-operand RISC -- a few RISC machines fall into this category. In a typical three-operand RISC machines, all three operands must be registers, so explicit load/store instructions are needed. An instruction set with 32 registers requires 15 bits to encode three register operands, so this scheme is typically limited to instructions sets with 32-bit instructions or longer. Example: load a, reg1, load b, reg2, add reg1+reg2->reg3, store reg3,c;
more operands -- some CISC machines permit a variety of addressing modes that allow more than 3 register-based operands for memory accesses.

[edit] Machine language
Machine language is built up from discrete statements or instructions. Depending on the processing architecture, a given instruction may specify:
Particular registers for arithmetic, addressing, or control functions
Particular memory locations or offsets
Particular addressing modes used to interpret the operands
More complex operations are built up by combining these simple instructions, which (in a von Neumann machine) are executed sequentially, or as otherwise directed by control flow instructions.
Some operations available in most instruction sets include:
moving
set a register (a temporary "scratchpad" location in the CPU itself) to a fixed constant value
move data from a memory location to a register, or vice versa. This is done to obtain the data to perform a computation on it later, or to store the result of a computation.
read and write data from hardware devices
computing
add, subtract, multiply, or divide the values of two registers, placing the result in a register
perform bitwise operations, taking the conjunction/disjunction (and/or) of corresponding bits in a pair of registers, or the negation (not) of each bit in a register
compare two values in registers (for example, to see if one is less, or if they are equal)
affecting program flow
jump to another location in the program and execute instructions there
jump to another location if a certain condition holds
jump to another location, but save the location of the next instruction as a point to return to (a call)
Some computers include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:
saving many registers on the stack at once
moving large blocks of memory
complex and/or floating-point arithmetic (sine, cosine, square root, etc.)
performing an atomic test-and-set instruction
instructions that combine ALU with an operand from memory rather than a register
A complex instruction type that has become particularly popular recently is the SIMD or Single-Instruction Stream Multiple-Data Stream operation or vector instruction, an operation that performs the same arithmetic operation on multiple pieces of data at the same time. SIMD have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as MMX, 3DNow! and AltiVec.
The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. One using CISC or complex instruction set computer where many instructions were implemented. In the 1970s places like IBM did research and found that many instructions were used that could be eliminated. The result was the RISC, reduced instruction set computer, architecture which uses a smaller set of instructions. The result was a simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption; a more complex one may optimize common operations, improve memory/cache efficiency, or simplify programming.

[edit] List of ISAs
This list is far from comprehensive as old architectures are abandoned and new ones invented on a continual basis. There are many commercially available microprocessors and microcontrollers implementing ISAs in all shapes and sizes. Customised ISAs are also quite common in some applications, e.g. ARC International, application-specific integrated circuit, FPGA, and reconfigurable computing. Also see history of computing hardware.

[edit] ISAs implemented in hardware
Alpha
ARM
Burroughs B5000/B6000/B7000 series
IA-64 (Itanium)
MIPS
Motorola 68k
PA-RISC
IBM 700/7000 series
System/360
System/370
System/390
z/Architecture
Power Architecture
POWER
PowerPC
PDP-11
VAX
SPARC
SuperH
Tricore
Transputer
UNIVAC 1100/2200 series
x86
IA-32 (i386, Pentium, Athlon)
x86-64 (64-bit superset of IA-32)
EISC (AE32K)

[edit] ISAs commonly implemented in software with hardware incarnations
p-Code (UCSD p-System Version III on Western Digital Pascal MicroEngine)
Java virtual machine (ARM Jazelle, PicoJava, JOP)
FORTH

[edit] ISAs never implemented in hardware
ALGOL object code
SECD machine, a virtual machine used for some functional programming languages.
MMIX, a teaching machine used in Donald Knuth's The Art of Computer Programming
Z-machine, a virtual machine used for Infocom's text adventure games

[edit] See also

[edit] Categories of ISA
CISC
RISC
VLIW
MISC
EPIC
vector processor
SIMD
Flynn's Taxonomy
orthogonal instruction set

[edit] Applications where specialized instruction sets are used
digital signal processor
graphics processing unit
reconfigurable computing

[edit] Device types that implement some ISA
central processing unit
microcontroller
microprocessor

[edit] Others
computer architecture
CPU design
emulator
hardware abstraction layer
Register Transfer Language
virtual machine
Atmel AVR instruction set
Streaming SIMD Extensions (SSE) instruction set
SSE2 IA-32 SIMD instruction set
Application binary interface

[edit] References
^ Ganssle, Jack. "Proactive Debugging". Published February 26, 2001.

[edit] External links
Mark Smotherman's Historical Computer Designs Page
Microprocessor Instruction Set Cards
A Set of Standard Microprocessor Programming Cards by Jonathan Bowen
Randy Hyde's discussion on ISA
[hide]
v • d • eCPU technologies
Architecture
Instruction Set Architecture · RISC · CISC · EPIC · VLIW · OISC · ZISC · Harvard architecture · Von Neumann architecture
Parallelism
Instruction pipelining · Superscalar · Out-of-order execution · Register renaming · Speculative execution · Multithreading · Multiprocessing
Components
ALU · FPU · Vector processor · SIMD · 32-bit/64-bit · Registers · Cache · ASIC · FPGA · DSP · Microcontroller · ASIP · SoC
Power conservation
Dynamic frequency scaling · Dynamic voltage scaling · Clock gating
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